On the Convergence Speed of Turbo Demodulation with Turbo Decoding

Iterative processing is widely adopted nowadays in modern wireless receivers for advanced channel codes like turbo and LDPC codes. Extension of this principle with an additional iterative feedback loop to the demapping function has proven to provide substantial error performance gain. However, the adoption of iterative demodulation with turbo decoding is constrained by the additional implied implementation complexity, heavily impacting latency and power consumption. In this paper, we analyze the convergence speed of these combined two iterative processes in order to determine the exact required number of iterations at each level. Extrinsic information transfer (EXIT) charts are used for a thorough analysis at different modulation orders and code rates. An original iteration scheduling is proposed reducing two demapping iterations with reasonable performance loss of less than 0.15 dB. Analyzing and normalizing the computational and memory access complexity, which directly impact latency and power consumption, demonstrates the considerable gains of the proposed scheduling and the promising contributions of the proposed analysis.Comment: Submitted to IEEE Transactions on Signal Processing on April 27, 201

Analysis of the Convergence Process by EXIT Charts for Parallel Implementations of Turbo Decoders

International audienceIterative process is a general principle in decoding powerful FEC codes such as turbo codes. However, the mutual information exchange during the iterative process is not easy to analyze and to describe. A useful technique to help the designer is the EXtrinsic Information Transfer (EXIT) chart. Unfortunately, this method cannot be directly applied to the decoding convergence analysis if parallel processing has to be exploited for the design of turbo decoders. In this letter, an extension of the EXIT charts method is proposed in order to take into account the constraints introduced by parallel implementations. The corresponding analysis associated with Monte-Carlo simulations gives additional understanding of the convergence process for the design of parallel architectures dedicated to turbo decoding

Convergence and Complexity Analysis of Turbo Demodulation with Turbo Decoding

International audienceConvergence speed analysis is crucial in TBICM-ID-SSD systems in order to tune the number of iterations when considering the practical implementation perspectives.Conducted analysis has demonstrated that omitting two turbo demodulation iterations without decreasing the total number of turbo decoding iterations leads to promising complexity reductions while keeping error rate performance almost unaltered.In the same context, promising results have been recently obtained when considering a feedback loop to the SISO equalizer for MIMO systems. Future work targets the extension of this analysis to other base-band iterative applications and its integration into available hardware prototypes

ASIP Design and Prototyping for Wireless Communication Applications

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High speed low complexity radix-16 Max-Log-MAP SISO decoder

International audienceAt present, the main challenge for hardware implementation turbo decoders is to achieve the high data rates required by current and future communication system standards. In order to address this challenge, a low complexity radix-16 SISO decoder for the Max-Log- MAP algorithm is proposed in this paper. Based on the elimination of parallel paths in the radix-16 trellis diagram, architectural solutions to reduce the hardware complexity of the different blocks of a SISO decoder are detailed. Moreover, two complementary techniques are introduced order to overcome BER/FER performance degradation when turbo decoders based on the proposed SISO decoder are considered. Thus, a penalty lower than 0.05dB is observed for a 8 state binary turbo code with respect to a traditional radix-2 turbo decoder for 6 decoding iterations

A Space-Time Redundancy Technique for Embedded Stochastic Error Correction

International audienceAn error-correction algorithm, referred as to Low Density Parity Check (LDPC) stochastic decoding technique, has recently been introduced for implementing iterative LDPC decoders in logic technologies with a high rate of transient faults. In this work, a modified algorithm that includes a feedback mechanism is first presented. A temporal majority logic is also applied at the decoder's output, providing an additional dimension of redundancy. By comparison to Gallager-A decoding method, the combination of feedback with temporal redundancy is shown to significantly increase the decoder's resilience against a high rate of internal upsets as a gain of up to three orders of magnitude

A highly parallel Turbo Product Code decoder without interleaving resource

International audienceThis article presents an innovative turbo product code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration turbo decoder of a (32,26)2 BCH product code, synthetized in a 90 nm CMOS technology, the resulting information throughput is 2.5 Gb/s with an area of 233 Kgates. Finally a second architecture enhancing parallelism rate is described. The information throughput is 33.7 Gb/s while an area estimation gives A=10 mum2

Scarce state transition turbo decoding based on re-encoding combined with a dummy insertion

International audienceAn efficient way to reduce the dynamic power dissipation in the turbo decoder is presented. This technique is based on a dynamic re-encoding of the received messages. The idea is to decrease the state transition activity of the trellis-based algorithms by replacing the classical direct decoding of the random noisy codewords by an equivalent decoding of an almost “all zero” codewords in order to keep the survivor path on the “zero path”

Techniques and Prospects for Fault-tolerance in Post-CMOS ULSI

International audienceThis paper presents a survey of fault-masking techniques suitable for tolerating short-duration transient upsets in minimum-scale switching devices. Two types of fault masking are considered. The first type, coded dual-modular redundancy (cDMR), represents a family of parity-checking methods suitable for correcting a low rate of transient upsets. The second type, Restorative Feedback (RFB), is a triple-modular solution suitable for compensating a higher rate of transient upsets. We show that cDMR can be used efficiently for crossbar-style logic, but is not efficient in general for all logic styles. By contrast, RFB offers a fixed redundancy, and can be applied in general to any logic circuit. Finally, we propose novel circuits for ternary Muller C implementation based on carbon nanotube FET devices

Flexible Multi-ASIP SoC for Turbo/LDPC Decoder

International audienceIn order to meet flexibility and performance constraints of current and future digital communication applications, multiple ASIPs combined with dedicated communication and memory architectures are required. In this work we consider the design of an innovative universal channel decoder architecture model by unifying flexibility-oriented and optimization-oriented approaches. Towards this objective, we have designed a flexible and scalable multiprocessor platform based on a novel ASIP architecture for high throughput turbo/LDPC decoding. The proposed platform supports turbo and LDPC codes of most emerging wireless communication standards (WiFi, WiMax, LTE, and DVB-RCS). Energy-aware optimisation techniques have been also proposed and implemented. Finally, a fully functional FPGA demonstrator is available and the proposed Multi-ASIP architecture has been successfully integrated into a new generation telecom chip